usbcore.tx package

Submodules

usbcore.tx.bitstuff module

class usbcore.tx.bitstuff.TxBitstuffer(*args, **kwargs)

Bases: usbcore.tx.bitstuff.TxBitstuffer

Bitstuff Insertion

Long sequences of 1’s would cause the receiver to lose it’s lock on the transmitter’s clock. USB solves this with bitstuffing. A ‘0’ is stuffed after every 6 consecutive 1’s.

The TxBitstuffer is the only component in the transmit pipeline that can delay transmission of serial data. It is therefore responsible for generating the bit_strobe signal that keeps the pipe moving forward.

https://www.pjrc.com/teensy/beta/usb20.pdf, USB2 Spec, 7.1.9 https://en.wikipedia.org/wiki/Bit_stuffing

usb_12 : 48MHz

i_data : Signal(1)

Data bit to be transmitted on USB.

o_data : Signal(1)

Data bit to be transmitted on USB.

o_stall : Signal(1)

Used to apply backpressure on the tx pipeline.

get_fragment()

usbcore.tx.bitstuff_test module

class usbcore.tx.bitstuff_test.TestTxBitstuffer(methodName='runTest')

Bases: usbcore.test.common.BaseUsbTestCase

test_passthrough()

test_passthrough_se0()

test_bitstuff()

test_bitstuff_input_stall()

test_bitstuff_se0()

test_bitstuff_at_eop()

test_multi_bitstuff()

do(**test_args)

usbcore.tx.crc module

class usbcore.tx.crc.TxSerialCrcGenerator(*args, **kwargs)

Bases: usbcore.tx.crc.TxSerialCrcGenerator

Transmit CRC Generator

TxSerialCrcGenerator generates a running CRC.

https://www.pjrc.com/teensy/beta/usb20.pdf, USB2 Spec, 8.3.5 https://en.wikipedia.org/wiki/Cyclic_redundancy_check

Parameters:

• are passed in via the constructor. (Parameters) –
• width (int) – Width of the CRC.
• polynomial (int) – CRC polynomial in integer form.
• initial (int) – Initial value of the CRC register before data starts shifting in.
• Ports (Output) –
• ------------ –
• i_data (Signal(1)) – Serial data to generate CRC for.
• Ports –
• ------------ –
• o_crc (Signal(width)) – Current CRC value.

get_fragment()

usbcore.tx.crc.bytes_to_int(d)

Convert a list of bytes to an int

Bytes are in LSB first.

>>> hex(bytes_to_int([0, 1]))
'0x100'
>>> hex(bytes_to_int([1, 2]))
'0x201'

usbcore.tx.crc.cols(rows)

>>> a = [
...  [1, 2],
...  ['a', 'b'],
...  [4, 5],
... ]
>>> for c in cols(a):
...   print(c)
[1, 'a', 4]
[2, 'b', 5]
>>> a = [
...  [1, 2, 3],
...  ['a', 'b', 'c'],
... ]
>>> for c in cols(a):
...   print(c)
[1, 'a']
[2, 'b']
[3, 'c']

usbcore.tx.crc.lfsr_serial_shift_crc(lfsr_poly, lfsr_cur, data)

shift_by == num_data_bits len(data_cur) == num_data_bits >>> for i in range(5): … l = [0]*5; l[i] = 1 … r = lfsr_serial_shift_crc( … lfsr_poly=[0,0,1,0,1], # (5, 2, 0) … lfsr_cur=l, … data=[0,0,0,0], … ) … print(“Min[%i] =” % i, r) Min[0] = [1, 0, 0, 0, 0] Min[1] = [0, 0, 1, 0, 1] Min[2] = [0, 1, 0, 1, 0] Min[3] = [1, 0, 1, 0, 0] Min[4] = [0, 1, 1, 0, 1] >>> for i in range(4): … d = [0]*4; d[i] = 1 … r = lfsr_serial_shift_crc( … lfsr_poly=[0,0,1,0,1], # (5, 2, 0) … lfsr_cur=[0,0,0,0,0], … data=d, … ) … print(“Nin[%i] =” % i, r) Nin[0] = [0, 0, 1, 0, 1] Nin[1] = [0, 1, 0, 1, 0] Nin[2] = [1, 0, 1, 0, 0] Nin[3] = [0, 1, 1, 0, 1]

usbcore.tx.crc.print_matrix(crc_width, cols_nin, cols_min)

>>> crc_width = 5
>>> data_width = 4
>>> poly_list = [0, 0, 1, 0, 1]
>>> _, cols_nin, cols_min = build_matrix(poly_list, data_width)
>>> print_matrix(crc_width, cols_nin, cols_min)
   0 d[ 0],      ,      , d[ 3],      , c[ 1],      ,      , c[ 4]
   1      , d[ 1],      ,      ,      ,      , c[ 2],      ,
   2 d[ 0],      , d[ 2], d[ 3],      , c[ 1],      , c[ 3], c[ 4]
   3      , d[ 1],      , d[ 3],      ,      , c[ 2],      , c[ 4]
   4      ,      , d[ 2],      , c[ 0],      ,      , c[ 3],

usbcore.tx.crc.build_matrix(lfsr_poly, data_width)

>>> print("\n".join(build_matrix([0,0,1,0,1], 4)[0]))
lfsr([0, 0, 1, 0, 1], [0, 0, 0, 0, 0], [1, 0, 0, 0]) = [0, 0, 1, 0, 1]
lfsr([0, 0, 1, 0, 1], [0, 0, 0, 0, 0], [0, 1, 0, 0]) = [0, 1, 0, 1, 0]
lfsr([0, 0, 1, 0, 1], [0, 0, 0, 0, 0], [0, 0, 1, 0]) = [1, 0, 1, 0, 0]
lfsr([0, 0, 1, 0, 1], [0, 0, 0, 0, 0], [0, 0, 0, 1]) = [0, 1, 1, 0, 1]
<BLANKLINE>
lfsr([0, 0, 1, 0, 1], [1, 0, 0, 0, 0], [0, 0, 0, 0]) = [1, 0, 0, 0, 0]
lfsr([0, 0, 1, 0, 1], [0, 1, 0, 0, 0], [0, 0, 0, 0]) = [0, 0, 1, 0, 1]
lfsr([0, 0, 1, 0, 1], [0, 0, 1, 0, 0], [0, 0, 0, 0]) = [0, 1, 0, 1, 0]
lfsr([0, 0, 1, 0, 1], [0, 0, 0, 1, 0], [0, 0, 0, 0]) = [1, 0, 1, 0, 0]
lfsr([0, 0, 1, 0, 1], [0, 0, 0, 0, 1], [0, 0, 0, 0]) = [0, 1, 1, 0, 1]
<BLANKLINE>
Mout[4] = [0, 0, 1, 0] [1, 0, 0, 1, 0]
Mout[3] = [0, 1, 0, 1] [0, 0, 1, 0, 1]
Mout[2] = [1, 0, 1, 1] [0, 1, 0, 1, 1]
Mout[1] = [0, 1, 0, 0] [0, 0, 1, 0, 0]
Mout[0] = [1, 0, 0, 1] [0, 1, 0, 0, 1]

class usbcore.tx.crc.TxParallelCrcGenerator(*args, **kwargs)

Bases: usbcore.tx.crc.TxParallelCrcGenerator

Transmit CRC Generator

TxParallelCrcGenerator generates a running CRC.

https://www.pjrc.com/teensy/beta/usb20.pdf, USB2 Spec, 8.3.5 https://en.wikipedia.org/wiki/Cyclic_redundancy_check

Parameters:

• are passed in via the constructor. (Parameters) –
• width (int) – Width of the CRC.
• polynomial (int) – CRC polynomial in integer form.
• initial (int) – Initial value of the CRC register before data starts shifting in.
• Ports (Output) –
• ------------ –
• i_data_payload (Signal(8)) – Byte wide data to generate CRC for.
• i_data_strobe (Signal(1)) – Strobe signal for the payload.
• Ports –
• ------------ –
• o_crc (Signal(width)) – Current CRC value.

get_fragment()

class usbcore.tx.crc.TxCrcPipeline

Bases: migen.fhdl.module.Module

usbcore.tx.crc_test module

class usbcore.tx.crc_test.TestTxSerialCrcGenerator(methodName='runTest')

Bases: usbcore.test.common.BaseUsbTestCase

test_token_crc5_zeroes()

test_token_crc5_zeroes_alt()

test_token_crc5_nonzero()

test_token_crc5_nonzero_stall()

test_data_crc16_nonzero()

do(**test_args)

class usbcore.tx.crc_test.TestTxParallelCrcGenerator(methodName='runTest')

Bases: usbcore.test.common.BaseUsbTestCase

sim(name, dut, in_data, expected_crc)

sim_crc16(in_data)

sim_crc5(in_data)

test_token_crc5_zeroes()

test_token_crc5_nonzero1()

test_data_crc16_nonzero1()

test_data_crc16_nonzero2()

class usbcore.tx.crc_test.TestCrcPipeline(methodName='runTest')

Bases: usbcore.test.common.BaseUsbTestCase

maxDiff = None

sim(data)

test_00000001_byte()

test_10000000_byte()

test_00000000_byte()

test_11111111_byte()

test_10101010_byte()

test_zero_bytes()

test_sequential_bytes()

test_sequential_bytes2()

test_sequential_bytes3()

usbcore.tx.nrzi module

class usbcore.tx.nrzi.TxNRZIEncoder

Bases: migen.fhdl.module.Module

NRZI Encode

In order to ensure there are enough bit transitions for a receiver to recover the clock usb uses NRZI encoding. This module processes the incoming dj, dk, se0, and valid signals and decodes them to data values. It also pipelines the se0 signal and passes it through unmodified.

https://www.pjrc.com/teensy/beta/usb20.pdf, USB2 Spec, 7.1.8 https://en.wikipedia.org/wiki/Non-return-to-zero

usb_48 : 48MHz

i_valid : Signal(1)

Qualifies oe, data, and se0.

i_oe : Signal(1)

Indicates that the transmit pipeline should be driving USB.

i_data : Signal(1)

Data bit to be transmitted on USB. Qualified by o_valid.

i_se0 : Signal(1)

Overrides value of o_data when asserted and indicates that SE0 state should be asserted on USB. Qualified by o_valid.

o_usbp : Signal(1)

Raw value of USB+ line.

o_usbn : Signal(1)

Raw value of USB- line.

o_oe : Signal(1)

When asserted it indicates that the tx pipeline should be driving USB.

usbcore.tx.nrzi_test module

class usbcore.tx.nrzi_test.TestTxNRZIEncoder(methodName='runTest')

Bases: usbcore.test.common.BaseUsbTestCase

test_setup_token()

do(**test_args)

usbcore.tx.pipeline module

class usbcore.tx.pipeline.TxPipeline

Bases: migen.fhdl.module.Module

usbcore.tx.pipeline_test module

class usbcore.tx.pipeline_test.TestTxPipeline(methodName='runTest')

Bases: usbcore.test.common.BaseUsbTestCase

maxDiff = None

pkt_decode_test(vector, name)

test_usb2_sof_token()

test_usb2_sof_token_bad_pid()

test_usb2_sof_token_bad_crc5()

test_usb2_ack_handshake()

test_usb2_ack_handshake_pid_error()

test_usb2_data_with_good_crc16()

test_usb2_data_with_bad_crc16()

usbcore.tx.shifter module

class usbcore.tx.shifter.TxShifter(*args, **kwargs)

Bases: usbcore.tx.shifter.TxShifter

Transmit Shifter

TxShifter accepts parallel data and shifts it out serially.

Parameters:

• are passed in via the constructor. (Parameters) –
• width (int) – Width of the data to be shifted.
• Ports (Output) –
• ----------- –
• ports are passed in via the constructor. (Input) –
• i_data (Signal(width)) – Data to be transmitted.
• Ports –
• ------------ –
• ports are data members of the module. All outputs are flopped. (Output) –
• o_data (Signal(1)) – Serial data output.
• o_empty (Signal(1)) – Asserted the cycle before the shifter loads in more i_data.
• o_get (Signal(1)) – Asserted the cycle after the shifter loads in i_data.

get_fragment()

usbcore.tx.shifter_test module

class usbcore.tx.shifter_test.TestTxShifter(methodName='runTest')

Bases: usbcore.test.common.BaseUsbTestCase

shifter_test(vector, name)

test_basic_shift_out_1()

test_basic_shift_out_2()

test_basic_shift_out_3()

test_stall_shift_out_1()

test_stall_shift_out_2()

test_stall_shift_out_3()

test_multistall_shift_out_1()

test_multistall_shift_out_2()

test_multistall_shift_out_3()

usbcore.tx.tester module

usbcore.tx.tester.get_ultimate_caller_modulename()

Helper to find the ultimate caller’s module name (extra level further up stack than case where test directly inherits from BaseUsbTestCase).

usbcore.tx.tester.create_tester(dut_type, **def_args)

usbcore.tx.tester.module_tester(dut_type, **def_args)

Module contents