usbcore.sm package

Submodules

usbcore.sm.header module

class usbcore.sm.header.PacketHeaderDecode(rx)[source]

Bases: migen.fhdl.module.Module

usbcore.sm.header_test module

class usbcore.sm.header_test.TestPacketHeaderDecode(methodName='runTest')[source]

Bases: usbcore.test.common.BaseUsbTestCase

sim(stim)[source]
recv_packet(dut, bits, tick)[source]
check_packet(expected_pid, expected_addr, expected_endp, packet)[source]
check_token(expected_pid, expected_addr, expected_endp)[source]
check_data(expected_pid, data)[source]
check_status(expected_pid)[source]
check_handshake(expected_pid)[source]
test_decode_setup_zero()[source]
test_decode_in_ep1()[source]
test_decode_out_ep8()[source]
test_decode_data0()[source]
test_decode_data1()[source]
test_decode_ack()[source]
test_decode_nak()[source]

usbcore.sm.send module

class usbcore.sm.send.TxPacketSend(tx, auto_crc=True)[source]

Bases: migen.fhdl.module.Module

usbcore.sm.send_test module

class usbcore.sm.send_test.CommonTxPacketSendTestCase[source]

Bases: object

maxDiff = None
assert_packet_sent(dut, pid, data=None, ndata=None)[source]
wait_for_packet(dut, tick_data=None)[source]
test_ack()[source]
test_nak()[source]
test_stall()[source]
test_status0()[source]
test_status1()[source]
test_data0_one_zero()[source]
test_data0_one_one()[source]
test_data0_two_ones()[source]
test_data0_edges()[source]
test_data0_all_zero()[source]
test_data0_dat1234()[source]
test_data1_all_zero()[source]
test_data0_descriptor()[source]
class usbcore.sm.send_test.TestTxPacketSendNoCrc(methodName='runTest')[source]

Bases: usbcore.test.common.BaseUsbTestCase, usbcore.sm.send_test.CommonTxPacketSendTestCase

maxDiff = None
sim(pid, data=None)[source]
class usbcore.sm.send_test.TestTxPacketSendAutoCrc(methodName='runTest')[source]

Bases: usbcore.test.common.BaseUsbTestCase, usbcore.sm.send_test.CommonTxPacketSendTestCase

maxDiff = None
sim(pid, data=None)[source]

usbcore.sm.transfer module

class usbcore.sm.transfer.UsbTransfer(iobuf, auto_crc=True)[source]

Bases: migen.fhdl.module.Module

usbcore.sm.transfer_test module

class usbcore.sm.transfer_test.TestUsbTransfer(methodName='runTest')[source]

Bases: usbcore.test.common.BaseUsbTestCase, usbcore.test.common.CommonUsbTestCase, usbcore.test.clock.CommonTestMultiClockDomain, unittest.case.TestCase

maxDiff = None
setUp()[source]

Hook method for setting up the test fixture before exercising it.

run_sim(stim)[source]
tick_sys()[source]
tick_usb48()[source]
tick_usb12()[source]
on_usb_48_edge()[source]
on_usb_12_edge()[source]
update_internal_signals()[source]
trigger(epaddr)[source]
pending(epaddr)[source]
clear_pending(epaddr)[source]
response(epaddr)[source]
set_response(epaddr, v)[source]
set_data(epaddr, data)[source]

Set an endpoints buffer to given data to be sent.

expect_data(epaddr, data)[source]

Expect that an endpoints buffer has given contents.

dtb(epaddr)[source]

Module contents