usbcore.cpu package

Submodules

usbcore.cpu.dummyusb module

class usbcore.cpu.dummyusb.DummyUsb(iobuf, debug=False, vid=4617, pid=23536, product='Fomu Bridge', manufacturer='Foosn')

Bases: migen.fhdl.module.Module

Implements a device that simply responds to the most common SETUP packets. It is intended to be used alongside the Wishbone debug bridge.

usbcore.cpu.epfifo module

class usbcore.cpu.epfifo.FakeFifo

Bases: migen.fhdl.module.Module

class usbcore.cpu.epfifo.Endpoint

Bases: migen.fhdl.module.Module, litex.soc.interconnect.csr.AutoCSR

class usbcore.cpu.epfifo.EndpointNone

Bases: migen.fhdl.module.Module

class usbcore.cpu.epfifo.EndpointOut

Bases: usbcore.cpu.epfifo.Endpoint

Endpoint for Host->Device data.

Raises packet IRQ when new packet has arrived. CPU reads from the head CSR to get front data from FIFO. CPU writes to head CSR to advance the FIFO by one.

class usbcore.cpu.epfifo.EndpointIn

Bases: usbcore.cpu.epfifo.Endpoint

Endpoint for Device->Host data.

Reads from the buffer memory. Raises packet IRQ when packet has been sent. CPU writes to the head CSR to push data onto the FIFO.

class usbcore.cpu.epfifo.PerEndpointFifoInterface(iobuf, endpoints=[<EndpointType.BIDIR: 3>, <EndpointType.IN: 1>, <EndpointType.BIDIR: 3>], debug=False)

Bases: migen.fhdl.module.Module, litex.soc.interconnect.csr.AutoCSR

Implements a CPU interface with each endpoint having it’s own FIFO.

Each endpoint has;

• A FIFO with one end connected to CSRs and the other to the USB core.
• Control bits.
• A pending flag.

An output FIFO is written to using CSR registers. An input FIFO is read using CSR registers.

Extra CSR registers set the response type (ACK/NAK/STALL).

usbcore.cpu.epmem module

class usbcore.cpu.epmem.MemInterface(iobuf, num_endpoints=3, depth=512)

Bases: migen.fhdl.module.Module, litex.soc.interconnect.csr.AutoCSR

Interfaces the USB state machine core to the soft CPU.

This interface has two memory regions:

• Output memory. Writable by CPU, readable by USB Core.
• Input memory. Writable by USB Core, readable by CPU.

Each endpoint has:

• A current pointer
• A current length
• Control bits
• A pending flag

Pointers are all relative to the start of the memory.

On output endpoints, both the pointer and length are read only. On input endpoints, the pointer and length are writable.

To accept / send data from an endpoint you set the arm bit. The USB core will then respond to the next request and update the pointer / length.

After a packet has been sent or received, the pending flag will be raised. While the pending flag is raised, the USB core will respond with NAK.

The arm, dtb, and sta registers are bitmasks. They are packed in pairs of IO. If you only have one endpoint, then arm, dtb, and sta are packed like this:

IO

Where

Bit 1 is set to affect EP0 IN, and Bit 0 is set to affect EP0 OUT

Likewise, if you have 3 endpoints, they are packed as:

IOIOIO |||||- EP0 OUT ||||– EP0 IN |||— EP1 OUT ||—- EP1 IN |—– EP2 OUT —— EP2 IN

Therefore, to ARM the EP1 IN endpoint, do:

arm_write((1<<1) | 1);

Or for EP2 IN:

arm_write((1<<2) | 1);

csr_bits(csr)

Work around the lack of bit-addressability in CSRs by creating an array of signals that are aliases of the various CSR storage values.

usbcore.cpu.eptri module

usbcore.cpu.unififo module

class usbcore.cpu.unififo.UsbUniFifo(iobuf)

Bases: migen.fhdl.module.Module, litex.soc.interconnect.csr.AutoCSR

Presents the USB data stream as two FIFOs via CSR registers.

usbcore.cpu.usbwishbonebridge module

class usbcore.cpu.usbwishbonebridge.USBWishboneBridge(usb_core, clk_freq=12000000, magic_packet=67)

Bases: migen.fhdl.module.Module